1. Technical Field
The present disclosure generally relates to the use of mechanical polishing and systems and methods therefor. In particular, the systems and methods disclosed are applicable to chemical-mechanical planarization (CMP) of semiconductor wafers and improving wafer-scale uniformity of CMP processes.
2. Description of the Related Art
CMP is a combination chemical and mechanical polishing technique used in the semiconductor industry to planarize the surface of a semiconductor wafer at various times during an integrated circuit fabrication process. Typically, it is desirable to planarize the wafer surface after completing deposition and patterning of one or more film layers, before proceeding to deposit a next layer of material. If planarization is omitted, uneven surface topography of the un-planarized surface can be transferred to, or accentuated in, subsequent layers.
Such non-uniform topography effects are more likely to occur if materials used in subsequent layers are conformal to the wafer and thus do not evenly fill surface recesses.
Non-uniform topography may occur on three different scales: wafer scale, die scale, and feature scale. Wafer-scale topography results from radial variation in the CMP process, from the center of a semiconductor wafer to the edge of the wafer. Wafer-scale topography can be addressed by adjusting CMP equipment parameters or materials used in the CMP process itself, so that, following a CMP step, the film thickness across the entire wafer is as uniform as possible.
A CMP process typically entails polishing the wafer surface using a rotating polishing pad and a slurry made from various chemicals and abrasive particulates, so that both chemical and physical removal mechanisms contribute to the planarization. Because the film has a different thickness at different locations on the wafer when it is deposited, it is desired to polish more at some locations on the wafer and less at other locations to achieve a final uniform film thickness on the entire wafer. Because the rotating pad in a conventional polisher system is typically larger than the wafer, changes made to the pad itself tend to affect the wafer as a whole i.e., changes to the pad affect “global uniformity.” Such changes are not effective in reducing localized variations in film thickness, or “local uniformity.”
As integrated circuit feature sizes shrink below 20 nm, both global and local CMP uniformity requirements become more stringent. If a film is not sufficiently flat across the entire wafer, it may fail to present a surface that remains in focus during a subsequent lithography step. Or, the pre-lithography alignment check may fail, causing a full wafer to be scrapped. Despite such consequences, conventional CMP systems lack the flexibility and the capability to address the local non-uniformity problem. Some compensatory solutions have been introduced at the lithography step. For example, a gas cluster ion beam (GCIB) can be used to treat individual die that have residues from previous steps, or die that have been under-polished. However, at a throughput of less than 10 wafers/hour, GCIB is a very slow and costly operation, and it is thus not a desirable approach to improving local uniformity.